Transactional memory

Results: 350



#Item
61Reducing contention in STM Panagiota Fatourou Department of Computer Science University of Crete & FORTH ICS  Mykhailo Iaremko1

Reducing contention in STM Panagiota Fatourou Department of Computer Science University of Crete & FORTH ICS Mykhailo Iaremko1

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Source URL: rp-www.cs.usyd.edu.au

Language: English
62A Formal Model of Crash Recovery in Distributed Software Transactional Memory (Extended Abstract) Paweł T. Wojciechowski, Jan Kończak Poznań University of TechnologyPoznań, Poland

A Formal Model of Crash Recovery in Distributed Software Transactional Memory (Extended Abstract) Paweł T. Wojciechowski, Jan Kończak Poznań University of TechnologyPoznań, Poland

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Source URL: rp-www.cs.usyd.edu.au

Language: English
63High Performance Hardware Transactional Memory does not Equal High Performance Transaction Systems Justin Levandoski (Microsoft) Darko Makreshanski (ETH Zurich) Ryan Stutsman (Utah)

High Performance Hardware Transactional Memory does not Equal High Performance Transaction Systems Justin Levandoski (Microsoft) Darko Makreshanski (ETH Zurich) Ryan Stutsman (Utah)

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Source URL: hpts.ws

Language: English - Date: 2015-10-02 08:07:40
64What is Safe in Transactional Memory Hagit Attiya1 Sandeep Hans1  Petr Kuznetsov2

What is Safe in Transactional Memory Hagit Attiya1 Sandeep Hans1 Petr Kuznetsov2

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Source URL: rp-www.cs.usyd.edu.au

Language: English - Date: 2012-07-13 04:06:54
65STN: A Robust and Distributed SDN Control Plane Marco Canini† , Daniele De Cicco† , Petr Kuznetsov‡ , Dan Levin• , Stefan Schmid? and Stefano Vissicchio†∗ † Universit´ e catholique de Louvain ‡ T´el´ec

STN: A Robust and Distributed SDN Control Plane Marco Canini† , Daniele De Cicco† , Petr Kuznetsov‡ , Dan Levin• , Stefan Schmid? and Stefano Vissicchio†∗ † Universit´ e catholique de Louvain ‡ T´el´ec

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Source URL: perso.uclouvain.be

Language: English - Date: 2014-02-26 05:33:20
66Good Programming in Transactional Memory Game Theory Meets Multicore Architecture Raphael Eidenbenz and Roger Wattenhofer Computer Engineering and Networks Laboratory (TIK), ETH Zurich, Switzerland {eidenbenz,wattenhofe

Good Programming in Transactional Memory Game Theory Meets Multicore Architecture Raphael Eidenbenz and Roger Wattenhofer Computer Engineering and Networks Laboratory (TIK), ETH Zurich, Switzerland {eidenbenz,wattenhofe

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Source URL: www.tik.ee.ethz.ch

Language: English - Date: 2015-05-18 12:16:06
67Euro-TM Workshop on Transactional Memory Bern, Switzerland, April 10, 2012 Differentiated Access to Virtual Resources in Cloud Environments

Euro-TM Workshop on Transactional Memory Bern, Switzerland, April 10, 2012 Differentiated Access to Virtual Resources in Cloud Environments

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Source URL: www.gsd.inesc-id.pt

Language: English - Date: 2012-04-18 12:46:07
68Tracing Snapshot Isolation in Transactions (Extended Abstract) Annette Bieniusa∗ Peter Thiemann†  Abstract

Tracing Snapshot Isolation in Transactions (Extended Abstract) Annette Bieniusa∗ Peter Thiemann† Abstract

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Source URL: rp-www.cs.usyd.edu.au

Language: English
69PolyCert: Polymorphic Self-Optimizing Replication for In-Memory Transactional Grids Maria Couceiro, Paolo Romano, Luis Rodrigues INESC-ID Instituto Superior Tecnico, Universidade Tecnica de Lisboa

PolyCert: Polymorphic Self-Optimizing Replication for In-Memory Transactional Grids Maria Couceiro, Paolo Romano, Luis Rodrigues INESC-ID Instituto Superior Tecnico, Universidade Tecnica de Lisboa

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Source URL: www.gsd.inesc-id.pt

Language: English - Date: 2012-02-23 10:35:12
70Bounds on Contention Management Algorithms Johannes Schneider Roger Wattenhofer  Johannes Schneider

Bounds on Contention Management Algorithms Johannes Schneider Roger Wattenhofer Johannes Schneider

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Source URL: disco.ethz.ch

Language: English - Date: 2014-09-26 08:36:50